Fluid control device



Aug. 29, 3967 E. M. DEXTER 3,338,515

FLUID CONTROL DEVICE Filed April 29, 1964 4 Sheets-Sheet l INVENTOR.EDWIN M. DEXTER ATTONEY Aug. 29, 3%? E. M. DEXTER 3,338,515

FLUID CONTROL DEVICE Filed April 29, 1964 4 Sheets5heet 2 Aug. 29, 1967E. M. DEXTER FLUID CONTROL DEVICE 4 Sheets-Sheet 3 Filed April 29, 1964wwl W m mw gm MOO d0 8 3967 E. M. DEXTER FLUID CONTROL DEVICE 4Sheets-Sheet Filed April 29, 1964 LOGIC FIG.5

FIRST STAGE FI 6.6- SHIFT REGISTER CIRCUIT USING DELAYS United StatesPatent ()fiflce 3,338,515 FLUID CONTROL DEVICE Edwin M. Dexter, SilverSpring, Md., assignor to General Electric Company, a corporation of NewYork Filed Apr. 29, 1964, Ser. No. 363,532 5 Claims. (Cl. 235-201)ABSTRACT OF THE DISCLOSURE A fluid system has a plurality of fluiddevices adapted to be maintained in one of two stable states. Each fluiddevice includes first and second fluid AND devices, with each AND devicehaving two input ports, first and second output legs. The AND deviceproduces an output on the first leg when an input signal is applied toone of the input ports and produces an output on the second leg wheninput signals are applied to both of the input ports. A fluid flip-flopincluded in each fluid device has a fluid power source, two output legs,a first input port connected to the second output leg of the first ANDdevice and a second input port connected to second output leg of thesecond AND device. The fluid flow from the source is directed into oneof the output legs until diverted into the other output leg upon theapplication of a fluid signal to the opposing input port. The stablestage of one fluid device is shifted to the next fluid device.

In another embodiment of the fluid system a delay is provided fordelaying the response of a succeeding fluid device to change the stateof a preceding fluid device until the previous state of the succeedingfluid device has been shifted.

This invention is directed to a fluid system composed of a plurality offluid control devices, and more particularly to a fluid system capableof representing binary information therein. In the specific embodimentdescribed herein the fluid system takes the form of a fluid controlledshift register operating in the binary form.

Very briefly then, a fluid system according to this invention comprisesa plurality of fluid devices adapted to be maintained in one of twostable states. The stable state in which a fluid device is maintainedmay be shifted to the next fluid circuit. In one embodiment of thisinvention two fluid devices are used for each stage of the shiftregister with the stable states in the first fluid device of each stageshifted to the second fluid device before being shifted to thesucceeding fluid shift register stage. In another embodiment only onefluid device is used for each stage of a shift register, with time delaymeans inserted between each fluid device to delay the response of asucceeding fluid device to changes in state of preceding fluid deviceuntil the previous state of the succeeding fluid device has beenshifted.

It is therefore an object of this invention to provide a new andimproved fluid system for representing binary information therein.

It is another object of this invention to provide a new and improvedfluid shift register for handling binary information.

Another object of this invention is to provide a new and improved fluidsystem which operates with only one fluid circuit for each shiftregister stage.

The invention is set forth with particularity in the appended claims.The principles and characteristics of the invention, as well as otherobjects and advantages are revealed and discussed through the medium ofthe illustrative embodiments appearing in the specification and drawingswhich follow.

In the drawings:

Patented Aug. 29, 1967 FIGURE 1, which consists of FIGURES 1a through 1gshows the fluid circuit used in this fluid system.

FIGURE 2 shows a planar view of a fluid logic circuit used in the fluidshift register circuit.

FIGURE 3 shows a planar View of the fluid amplifier used in the fluidshift register.

FIGURE 4 shows a schematic of a fluid shift register using two fluidcircuits for each stage of a fluid shift register, identified as asecondary storage shift register.

FIGURE 5 shows a planar view of a fluid logic circuit used in a fluidshift register using one fluid bistable circuit for each stage of afluid shift register.

FIGURE 6 is a schematic for a one fluid bistable element for each stageshift register using the fluid circuit shown in FIGURE 5, identified asa delay type shift register.

Logic elements For illustrative purposes, the fluid devices are shownwith open channels. Obviously in use the channels are closed with thefluid devices interconnected by either stacking them on each other withthe input and output ports registering with each other, or 'byinterconnecting the input and output ports by tubing.

The fluid devices used in this embodiment are shown in FIGURE 1. Fluiddevices have been designed to function as analog, logic, and digitaldevices. This embodiment uses only logic and digital devices.

The underlying principle of operation of the logic and digital fluiddevice is a Coanda effect which holds that a fluid jet will attach to awall placed adjacent to the fluid jet. In FIGURE 1a, a fluid jet M flowsfrom the power source S into the channel bounded by walls X and Y. Withtwo walls X and Y present, and with proper proportions, the fluid jet Mwill arbitrarily attach itself to one wall as it has attached itself towall X, and remain attached if undisturbed.

An input flow applied to port C does not disturb the fluid jet M,however, an input flow applied to port C will detach the fluid jet fromthe wall X, and the fluid jet M will move over and attach itself to wallY. The fluid jet M will remain attached to wall Y whether an input flowdoes or does not continue from input port C AND circuit The device shownin FIGURE 1b is a plan view of an AND circuit. FIGURE 10 shows thesymbolic representation for the AND circuit. Ports E and E are impedancematching ports, and do not enter into the logical operation of thedevice. When an input is applied to input port C alone, or to input portC alone, output flow occurs at output port P When there are inputs atboth input ports C and C an output flow occurs at output port P A planview of a flip-flop is shown in FIGURE 1d, and a symbolic representationof the flip-flop is shown in FIGURE 13. A continuous fluid jet from thepower source S attaches itself arbitrarily to one wall of the centralchannel directing the jet flow into one leg P or P to provide an outputfrom output port P or P An output flow app ied to input port C willcause the fluid jet to attach itself to wall X directing the jet flowfrom the input source S into leg P to provide an output signal from theoutput port P An input flow applied to input ports C will cause thefluid jet to attach itself to wall Y directing the jet flow from theinput source S into leg P to provide an output signal from the outputport P 0R circuit A plan view of an OR circuit is shown in FIGURE 1 anda symbolic representation of the OR circuit is shown in FIGURE 1g. Thefluid jet from the power source S is normally biased by a bias flow fromthe bias input B to attach itself to the wall Y of the central channelso that the fluid jet is directed into leg P providing an output signalfrom the output port P An input flow into port C or C both C and C willcause the fluid jet to detach itself from the wall X to direct the fluidjet into the P leg to provide an output signal from the P output port.When the input flow is removed from both of the input ports C and C thefluid jet returns to the Y wall under the control of the input bias flowfrom the bias port B to provide an output signal from the P port.

In the following description the terms signals and pulses will be usedto refer to fluid flows which are applied to input ports. The termsignal will be used when the fluid flow is maintained for some length oftime, and the term plus will be used when the fluid flow is applied toonly a relatively short period of time.

Secondary storage shift register Each shift register stage consists oftwo logic plates and two amplifier plates. The logic plate is laid outas shown in FIGURE 2, and the amplifier plate is laid out as shown inFIGURE 3.

Referring now to FIGURE 2, the logic for one storage circuit for a stageis shown laid out on a logic plate 11. The logic plate is formed ofsuitable material such as metal, plastic or the like, which is slottedin a special configuration to provide passages for fluid. The variousslots and configurations in the plate 11 may be formed in any suitablemanner and may extend entirely through the plate, or may be of lesserdepth as desired. In the illustrated embodiment, the slots in the plate11 are shown extending only partially therethrough. A covering plate ispositioned on the top side of the first plate to confine fluid to thevarious slots of the plate 11, and the plates are stacked on top of eachother to confine the fluid in the various slots and configurations. Thefluid utilized in the devices may assume a variety of forms. Forexample, the fluid may constitute a compressible fluid, such as air, toprovide a pneumatic device. As a further example the fluid may benoncompressible, such as oil or water, to provide a hydraulic device. Inthis specific embodiment the fluid is air to provide a pneumatic device.

Ports 13, 15, and 19, and S of flip-flop 21 extend entirely through thelogic plate 11 to the succeeding stacked amplifier and logic plates.Clock pulses are applied to ports 13 and 15 alternatively. Clock pulseport 13 is connected to channel 23 which connects to the C input portsof AND circuits 25 and 27. Clock pulse port 15 is not connected to logicplate 11. Power jet port 17 is not connected to the logic plate 11, butis connected to the amplifier flip-flop shown in FIGURE 3. The C inputterminals of AND circuits 25 and 27 are connected to the outputs of thepreceding amplifier. The E exhaust ports of AND circuits 25 and 27 areconnected to the outside atmosphere, and the E exhaust ports areconnected to a port 19 which is connected to the outside atmosphere. TheP output ports of AND circuits 25 and 27 are connected to the outsideatmosphere, the P output port of AND circuit 25 is connected to the Cinput port of flip-flop 21, and the P out-put port of AND circuit 27 isconnected to the C input port of flip-flop 21. The S fluid jet offlipflop 21 is connected to a fluid power source. The E and E exhaustports of flip-flop 21 are connected through the logic plate 11 to thepower amplifier stacked below the logic plate 11.

Referring now to FIGURE 3, ports 13, 15, 17, 18, and 19 are the sameports shown in FIGURE 2 and extend through the amplifier plate 29. Thefluid jet supply pressure manifolds (17) of the amplifier 31 isconnected to an outside fluid power source. The amplifier plate 29 isstacked between two logic plates 11 as shown in FIG- URE 2. In thismanner the input ports C and C of the amplifier 31 are connected to theoutput ports P and P of the flip-flop 21 on the logic plate 11 andstacked above the amplifier plate 29, and the output ports P and Prespectively, of the amplifier 31 are connected to the input ports C ofAND circuit 27 and input port C of AND circuit 25 on the logic plate 11in FIGURE 2 stacked below the amplifier 31. Exhaust ports E and E of theamplifier 31 are connected to the outside atmosphere.

The sealing gaskets are placed between the logic plates and theamplifier plates with proper holds therein to effect the indicatedconnection between the plates. The logic plates, the amplifier plates,and the gaskets are stacked to provide the proper interconnections.

The operation of the logic plate 11 in FIGURE 2 and the amplifier plate29 in FIGURE 3 will be described now as a one storage circuit of a shiftregister stage. Assume for the purpose of this description that an inputsignal applied to input port C of AND circuit 25 indicates a binary one,and an input signal applied to input port C of AND circuit 27 indicatesa binary Zero.

A signal applied to input port C of AND circuit 25 indicates a binaryone. A clock pulse is applied to the clock pulse port 13 at apredetermined period of time to apply a pulse to the C input ports ofAND circuits 25 and 27. As AND circuit 25 has a signal applied to its Cinput port at this time AND circuit 25 applies an output signal from itsP output port to the C input port of flip-flop 21. AND circuit 27 withno signal applied to its C input port continues to produce an output onits P output port which is exhausted to the outside atmosphere.

Flip-flop 21 with a signal applied to its C input port flips to itsbinary one state to produce an output signal from its P output port. Theoutput signal from the P output port of flip-flop 21 is applied to the Cinput port of the amplifier 31 in FIGURE 3 to switch that amplifier toits binary one state to produce an output signal from its P output port.The output signal from the P output port of the amplifier 31 is appliedto the C input port of the binary one AND circuit on the next logicplate.

A signal is applied to the C input port of AND circuit 27 causesflip-flop 21 to apply a signal from its P port to the C port ofamplifier 31 to switch this amplifier to its binary zero state.

Referring now to FIGURE 4, a schematic of a two stage shift register isshown. The fluid logic elements are shown in symbolic form as shown inFIGURE 1. Each stage consists of two storage circuits such as shown anddescribed in FIGURES 2 and 3. The first stage 33 has a first storagecircuit consisting of a flip-flop 35, two input AND circuits 37 and 39,and amplifier 41, shown schematically. The intermediate storage circuitof the first stage 33 consists of a flip-flop 42, two input AND circuits45 and 47, and amplifier 49.

The second stage 51 consists of two storage circuits. The first storagecircuit consists of a flip-flop 53, two input AND circuits 54 and 55,and amplifier 57. The intermediate storage circuit consists of aflip-flop 59, two input AND circuits 61 and 63, and amplifier 65.

Each storage circuit is connected in a manner shown and described withrelation to FIGURES 2 and 3. The C input port of each AND circuit isconnected to a clock pulse input port, and the C input ports areconnected to inputs or output ports of the preceding flip-flop. The Poutput ports are exhausted to the atmosphere. The P output ports of theAND circuits are connected to the input ports of the flipflop. Theoutput ports of the flipflop are connected through an amplifier to theinput ports of the AND circuits of the next storage circuit.

Input terminal 67 is a binary one terminal connected to the C ports ofAND circuit 39 in the first storage circuit of the first stage 33. Inputterminal 69 is a binary zeno terminal connected to the C port of ANDcircuit 37 in the first storage circuit of the first stage 33. Inputterminal '71 is a clock pulse 1 terminal which receives a clock pulse ata predetermined period of time and applies C input ports of AND theseclock pulse 1 pulses to the C ports of AND circuits 37 and 39 of thefirst storage circuit in the first stage 33,. and to the C ports of ANDcircuits 54 and 55 of the first storage circuit of the second stage 51.Input terminal 73 is a clock pulse 2 terminal which receives a clockpulse at a predetermined period of time after the clock pulse receivedon clock pulse 1 and applies this clock pulse 2 pulse to the C ports ofAND circuits 61 and 63 of the intermediate storage circuit in the secondshift register stage 51. A binary one output terminal 75 is connected tothe P output port of flip-flop 59 in the intermediate storage circuit ofthe second stage 51, and a binary zero output terminal 77 is connectedto the P output ports of flip-flop 59 through amplifier 65. A binaryoutput terminal 48 is connected to the P output port of flip-flop 43 anda binary zero output terminal 46 is connected to the P output port offlip-flop 43 through amplifier 49 in the intermediate storage circuit inthe first stage 33.

Operation Signals are applied to input terminals 67 or 69 depending onwhat binary number is to be entered into the two stage shift register.Assume that the shift register has been previously cleared so that eachstage 33 and 51 of the shift register is at a binary zero. Flip-flops35, 43, 53, and 59 therefore produce a signal from their P output ports.Amplifiers 41, 49, 57 and 65 invert the signals so that the zero outputterminal 46 from the first stage 33 produces a signal indicating thatthe first stage contains a binary zero, and the zero output terminal 77from the second stage 51 produces a signal indicating that the secondstage contains a binary zero.

Assume that two binary ones are to be shifted into the two stage shiftregister shown in FIGURE 4.

TABLE 1 Flip-Flops I 35 I 43 53 I 59 STAGE I I STAGE II FirstIntermediate First Intermediate Storage Storage Storage Storage Clock 1}1 0 0 Clock 2 1 1 O 0 Clock 1} l 1 1 0 Clock 2 1 1 1 1 Clock 1 3 0 1 1 1Clock 2 0 0 1 1 Clock 1} 0 0 0 1 Clock 2 0 0 0 0 Step 1, clock pulse 1 Asignal is applied to the binary one input terminal 67 applying a signalto the C port of AND circuit 39. At clock pulse time 1 of step 1 a clockpulse is applied to terminal 71 applying a pulse to input ports C of ANDcircuits 37 and 39, 'Of the first stage 33', and to input ports C of ANDcircuits 54 and 55 of the second stage 51. As AND circuit 39 has asignal applied to its C input port, AND circuit 39 applies an outputsignal from its P output to the C input port of flip-flop 35 to set thatflip-flop to a binary one, as shown in step 1, clock pulse 1 of Table 1.As soon as the clock AND circuit 39 stops producing a signal from its Poutput port, and produces a signal on'its P output port again. Flip-flop35, however, remains set to one, applies a signal from its P outputport, inverted by amplifier 41 and applied to the C input port of ANDcircuit 45.

Step 1, clock pulse 2 At clock pulse 2 of step I, a clock pulse isapplied to terminal 73, applying a pulse to the C input ports of ANDcircuits 45 and 47 of the first stage 33, and. to the circuits 61 and 63of the second stage 51. As the C input port of AND circuit 45 has apulse terminates signal applied thereto from the P output port offlip-flop 35 as inverted by amplifier 41. AND circuit 45 applies asignal to the C input port of flip-flop- 43 to set that flip-flop toone. AND circuit 45 stops producing an out signal from its P port assoon as the clock pulse finished. Blip-flops 35 and 43 are set to one atthis time as indicated in 'clock 2, step 1 of Table 1. Flip-flop 43applies a signal from its P output port which is inverted by amplifier49 and applied to the binary one output terminal 48 to indicate that thefirst stage 33 is set to one. The second stage remains reset to zero sothat a signal is applied from the zero output terminal 77.

Step 2, clock pulse 1 To shift in the second binary one, a signal isapplied to the binary one input terminal 67 applying a signal to the Cinput port of AND circuit 39. This signal may be applied anytime afterclock pulse 2 of step 1. At clock pulse 1 time or step 2, a clock pulseis applied to terminal 71, applying a pulse to the C input ports of ANDcircuits 37 and 39, stage 33, and the C input 55 of the second stage 51.AND circuit 39 has a signal applied to its C input port at this timefirom the input terminal 67 so it applies a signal from its P outputport to the C input port of flip-flop 35 to set that flip-flop to one.AND circuit 54 has a signal applied to its C input port from the Poutput port of flip-flop 43 as inverted by amplifier 49 at this time sothat it applies a signal from its P output port to the C input port offlip-flop 53 to set that flip-flop to one. AND circuits 39 and 54 stopproducing output signals as soon as clock pulse 2 terminates, butflip-flops 35 and 53 remain set to one, and flip-flop 43 is already setto one. Thus, at clock time 1, step 2, the flip-flops are indicated inTable 1.

Step 2, clock pulse 2 At clock pulse 2 time of step 2, a clock pulse isapplied to terminal 73, applying a pulse to the C input ports of ANDcircuits 45 and 47 of the first stage 33, and to the C input ports ofAND circuits 61 and 63 of the second stage 51. As the C input port ofAND circuit 45 has a signal applied thereto from the P output portflipflop as inverted by amplifier 41, AND circuit 45 applies a signal tothe C input port of flip-flop 43 to set that fiip-flop to one. The Cinput port of AND circuit 61 has a signal applied thereto from the Poutput port of flip-flop 53 as inverted by amplifier 57, so that ANDcircuit 61 applies a signal to the C input port of flip-flop 59 to setthat flip-flop to one. AND circuits 45 and 61 stop producing outputsignals as soon as clock pulse 2 terminates, but flip-flops 43 and 59remain set to one. Thus, after step 2, clock pulse 2, flip-flops 35, 53,43, 53, and 59 are set to one as shown in Table 1.

Output terminal 48 produces a signal indicating that the first stage 33is set to a binary one, and output terminal 75 produces a signalindicating that the second stage 51 is set to a binary one.

Step 3, clock pulse 1 A signal is applied to the binary zero inputterminal 69 app clock pulse 1 time of step 3 a clock pulse is applied toterminal 71, applying a pulse to the C input ports of AND circiuts 37and 39 of the first stage 33, and to the C input ports of AND circuits54 and 55 of the second stage 51. AND to its C input port at this timefrom the input terminal 69 so it applies a signal from 1118 P outputport to the C input port of flip-flop 35 to reset that flip-flop tozero. AND circuit 54 has a signal applied to its C input port from the Poutput port of flip-flop 43 through amplifier 49 so that it applies asignal from its P output port to the C input port of flip-flop 53 to setthat flip-flop to a binary one. AND circuits 39 and 45 stop producingoutput signals as soon as the clock pulse 2 terminates, but flip-flop 35remains reset to zero, and flip-flop 53 remains set to one. Flip-flops43 and 59 remain set to one. The state of the flip-flops in the twostages 33 and 51 is as indicated in Table 1, step 3, clock pulse 1.

Signals are applied to the zero input terminal 69 and clock pulsesapplied to the clock pulse input terminals 71 and 73 as described abovefor clock pulse 2 of step 3, and clock pulses 1 and 2 of step 4 to clearthe shift register as indicated in Table l. The operation of the shiftregister is as described above.

Logic plate layout for time delay shift register Referring now to FIGURE5, each shift register stage of a one flip-flop per bit using an RC timedelay between the stages consists of a logic plate 80. The logic plateis laid out as shown in FIGURE 5. The logic plate is similar to thatshown in FIGURE 2, With two AND circuits and a flip-flop, but differs inthe addition of two RC time delays. Restrictors and volumes produce anRC delay for incompressible fluids or gases; along line (Le. a sonicdelay) would be used for an incompressible fluid, or liquid.

Clock pulses are applied to the input port 81, which is connected bychannel 83 to the input C input ports of AND circuits 85 and 87. Zerosignals are applied to input port 89, through a restriction 91, througha volume chamber 93 to the C input port of AND circuit 85. One signalsare applied to input port 95, through a restriction 97, through a volumechamber 99, to the C input port of AND circuit 87. The restriction 91and volume chamber 93 act to delay the fluid pulse or signal applied toinput port 91 for a predetermined period of time depending on the sizeof the restriction 91 and the size of the volume chamber 93. Therestriction 97 and volume chamber 99 act to delay the fluid pulse ofsignal applied to input port 95 for a predetermined period of timedepending on the size of the restriction 97 and the size of the volumechamber 99.

The E exhaust ports of AND circuits 85 and 87 are connected to theoutside atmosphere, and the E exhaust ports of AND circuits 85 and 87are connected to port 101 which is connected to the outside atmosphere.The P output ports of AND circuits 8S and 87 are connected to theoutside atmosphere. The P output port of AND circuit 85 is connected tothe C input port of flip-flop 103, and the P output port of AND circuit87 is connected to the C input port of flip-flop 103. The E and Eexhaust ports of flip-flop 103 are connected to the outside atmosphere.The P and P output ports of flipflop 103 are connected to the inputports of an amplifier similar to that shown in FIGURE 3.

The logic plate for the one flip-flop per stage shift register using arestriction volume time delay between each flip-flop operates in thefollowing manner. The clock pulse applied to the clock pulse input port81 must last long enough to shift the information to that stage of theshift register, and should not last as long as the time delay imposed bythe restriction volume chamber.

A signal is applied to input port 89 or 95 depending on the state of theprevious stage of the shift register. Assume for the immediate purposesof this description that the previous stage of the shift register is setto one so that a signal has been applied to input port 95. This signalwas delayed a predetermined period of time by the restriction 97 and thechamber 99 before being applied to the C port of AND circuit 87. Atclock pulse time a clock pulse is applied to input port 81 applying apulse to the C input ports of AND circuits 85 and 87. As the C inputport of AND circuit 87 has a signal applied thereto at this time, ANDcircuit 87 applies a signal from its P output port to the C input portof flip-flop 103 to set that flip-flop to a binary one. Because of thedelay imposed on the output of flip-flop 103 by the restriction volumeof the next logic stage, the new state of flip-flop 103 is not appliedto the next stage of the shift register until after the clock pulseapplied thereto has finished. Also because of the time delay imposed bythe restrictions 91 and 97, and the volumes 93 and 99, the stage of thepreceeding stage of the shift register is not applied to AND circuitsand 87 until the clock pulse applied to the C input ports of ANDcircuits 85 and 87 has finished.

The above described operation is repeated with the application of thenext clock pulse to the input port 81. Only two stages are shown, butany number may be connected in series as shown.

One flip-flop per-stage shift-register Refer now to FIGURE 6 for adescription of a two stage shift register having only one flip-flop perstage, and using restriction-volume delay elements. Input signals areapplied to input terminal 109 for a binary zero. Input terminal 107 isconnected to the C input port and input terminal 109 is connected to theC input port of flip-flop 111. The P output port of flip-flop 111 isconnected through restriction 113 and volume chamber 115 to the C inputport of AND circuit 117. The P output port of flip-flop 111 is connectedthrough restriction 119 and volume chamber 121 to the C input port ofAND circuit 123. The P output port of AND circuit 117 is connected tothe C input port of flip-flop 125, and the P output port of AND circuits117 and 123 constitute the first stage 127.

The P output port of flip-flop 125 is connected through restriction 129and volume chamber 131 to the 0, input port of AND circuit 133. The Poutput port of flip-flop 125 is connected through restriction 135 andvolume chamher 137 to the C input port of AND circuit 139. The P outputport of AND circuit 133 is connected to the C input port of flip-flop141 and the P output port of AND circuit 139 is connected to the C inputport of flip-flop 141. Flip-flop 141, and AND circuits 133 and 139constitute the second stage 143-.

A one output terminal 145 is connected to the P output port of flip-flop141, and a zero output terminal 147 is connected to the P output port offlip-flop 141.

A binary one output terminal is connected to the P output port offlip-flop 125, and a binary zero output terminal 151 is connected to theP output port of flipflop 125 for the first stage 127. A binary oneoutput terminal 155 and a binary zero output terminal 153 are connectedto the P and the P output ports, respectively, of flip-flop 141 for thesecond stage 143.

Clock pulses applied to the clock pulse terminal 157 are applied to theC input ports of AND circuits 115, 123, 135 and 139.

Assume for the purposes of this immediate description that eachflip-flop 111 and 125 of the first stage 127, and 141 of the secondstage 143, are reset to zero as shown in step 1 of Table 2. Flip-flop111 applies a signal from its P output port to the C input port of ANDcircuit 117, flip-flop 125 applies a signal from its P output port tothe C input port of AND circuit 139, and flip-flop 141 applies a signalfrom its P output port to the zero output terminal 145.

Then assume that a signal is applied to the one input terminal 107applying a signal to the C input port of flip-flop 111 to set thatflip-flop to one. Flip-flop 111 then applies a signal from its P outputport, after a predetermined delay through restriction 119, and volumechamber 121, to the C input port of AND circuit 123. A clock pulse isthen applied to terminal 157 applying a pulse to the C input ports ofAND circuits 117, 123, 133, and 139. AND circuit 123 in the first stage127 and AND circuit 139 in the second stage have signals applied totheir C input ports at this time, AND circuit 123 therefore applies asignal from its P output port to the C input port of flip-flop 125 toset that flip-flop to one. AND circuit 139 applies a signal from its Poutput port to the C input port of flip-flop 141 to reset that flip-flopto zero. The first stage 127 is now set to one, and the second stage 143is reset to zero. A signal is delivered on output terminal 149indicating that the first stage is set to one and a signal is deliveredon output terminal 153 indicating that the second stage is reset tozero.

Before the next clock pulse a signal is applied to the one inputterminal 107 to set flip-flop 111 to one, applying a signal to the Cinput terminal of AND circuit 123 after a delay by the restriction 119and volume chamber 121. Flip-flop 125 is now set to one, so after thedelay by the restriction 129 and volume chamber 131, a signal is appliedto the C input port of AND circuit 133. At clock pulse time, a clockpulse is applied to terminal 157 applying signals to the C input portsof AND circuits 117, 123, 133 and 139. AND circuits 123 and 133 havesignals applied to their C input ports at this time so that AND circuit123 applies a signal to the C input port of flipflop 125 to set thatflip-flop to one, and AND circuit 1333 applies a signal to the C inputport of flip-flop 141 to set that flip-flop to one. Both stages 127 and143 are thus set to one, so that output terminal 149 produces a signalindicating that the first stage 127 is set to one and output terminal155 produces a signal indicating that the second stage 143 is set toone.

It can be seen that the function of the delay circuits consisting of arestriction and a volume chamber in the input circuit to the C ports ofthe AND circuits serves to delay the eflect of the change of thepreceding flip-flop until the effect of the previous setting of theflip-flop has been shifted to the next flip-flop by the application of aclock pulse.

Only two stages and an input flip-flop are shown in FIGURE 6. It shouldbe understood that any shift register may be constructed having largenumbers of stages by connecting them in the manner shown.

While the invention has been explained and described With the aid ofparticular embodiments thereof, it will be understood that the inventionis not limited thereby and that many modifications retaining andutilizing the spirit thereof without departing essentially therefromwill occur to those skilled in the art in applying the invention tospecific operating environments and conditions. It is thereforecontemplated by the appended claims to cover all such modifications asfall Within the scope and spirit of the invention.

What is claimed is:

1. A fluid system comprising, a plurality of fluid devices adapted to bemaintained in one of two stable states, each of said fluid devicesincluding a first and second fluid AND devices, each AND device havingtwo input ports, first and second output legs, said AND device producingan output on said first leg when an input signal is applied to one ofsaid input ports, and producing an output on said second leg when inputsignals are applied to both of said input ports, including a fluidflip-flop having a fluid power source, two output legs, a first inputport connected to said second output leg of said first AND device, and asecond input port connected to said second output leg of said second ANDdevice, with the fluid flow from the source directed into one of saidoutput legs until diverted into the other output leg upon theapplication of a fluid signal to the opposing input port, and means forshifting the stable stage of one fluid device to the next fluid device.

2. A fluid system comprising, a plurality of fluid devices, each of saidfluid devices having first and second fluid AND devices, said ANDdevices having two input ports, first and second output legs, said ANDdevices producing an output on said first leg when an input signal isapplied to one of said input ports, and producing an output on saidsecond leg when input signals are applied to both of said input ports,each of said fluid devices having a fluid flip-flop with a power source,first and second output legs, a first input port connected to saidsecond output leg of said first AND device, a second input portconnected to said second output leg of said second AND circuit, with thefluid flow from the source directed into said first output leg toestablish a first stable state upon the application of a signal to saidfirst input port and directed into said second output leg to establish asecond stable state upon the application of a signal to said secondinput port, and means for shifting the stable state of one fluid deviceto the next fluid device.

3. A fluid system comprising a plurality of fluid devices, adapted to bemaintained in one of two stable states, each of said fluid devicesincluding a first and second fluid AND devices, each AND device havingtwo input ports, first and second output legs, said AND device producingan output on said first leg when an input signal is applied to one ofsaid input ports, and producing an output on said second leg when inputsignals are applied to both of said input ports, including a fluidflip-flop having a fluid power source, two output legs, a first inputport connected to said second output leg of said first AND device, and asecond input port connected to said second output leg of said second ANDdevice, with the fluid flow from the source directed into one of saidoutput legs until diverted into the other output leg upon theapplication of a fluid signal to the opposing input port, means forshifting the stable state of one fluid device to the next fluid device,and means associated with each of said fluid devices for delaying theresponse of a succeeding fluid device to changes in state of a precedingfluid device until the previous state of the succeeding fluid device hasbeen shifted.

4. A fluid device comprising a plurality of fluid devices, adapted to bemaintained in one of two stable states, each of said fluid devicesincluding a first and second fluid AND devices, each AND device havingtwo input ports, first and second output legs, said AND device producingan output on said first leg When an input signal is applied to one ofsaid input ports, and producing an output on said second leg when inputsignals are applied to both of said input ports, including a fluidflip-flop having a fluid power source, two output legs, a first inputport connected to said second output leg of said first AND device, and asecond input port connected to said second output leg of said second ANDdevice, with the fluid flow from the source directed into one of saidoutput legs until diverted into the other output leg upon theapplication of a fluid signal to the opposing input port, means forshifting the stable state of one fluid device to the next fluid device,means for connecting said plurality of fluid devices in series, andmeans associated with each of said fluid devices for delaying theresponse of a succeeding fluid device to changes in state of a precedingfluid device until the previous state of the .suc ceeding fluid devicehas been shifted.

5. A fluid system comprising a plurality of fluid devices, adapted to bemaintained in one of two stable states, each of said fluid devicesincluding a first and second fluid AND devices, each AND device havingtwo input ports, first and second output legs, said AND device producingan output on said first leg when an input signal is applied to one ofsaid input ports, and producing an output on said second leg when inputsignals are applied to both of said input ports, including a fluidflip-flop having a fluid power source, two output legs, a first inputport connected to said second output leg of said first AND device, and asecond input port connected to said second output leg of said'second ANDdevice, with the fluid flow from the source directed into one of saidoutput legs until diverted into the other output leg upon theapplication of a fluid signal to the opposing input port, means forconnecting said plurality of fluid devices in series, means for shiftingthe stable state of one fluid device to the next succeeding fluiddevice, and a constriction and a chamber in said means connecting afluid device to a succeeding fluid device for delaying the response 1112 of a succeeding fluid device to changes in state of a pre- OTHERREFERENCES gl f g gi State of the H. D. L. Report, TR1114, FluidAmplification, Logic mg m as ms 6 elements #9, E. v. Hobbs, Mar. 3,1963, pp. 20, 21,

References Cited 5 22, 23 and 24. UNIT STATES PAT N Fluid Logic ShiftRegister With Intermediate Stages, 3,128,039 4/1964 Norwood I. B. M.Technical Disclosure Bulletin, H. R. Grubb, 3,193,197 7/1965 Bauer137-81,5 X June, 1963, V01. #6, N0. 1, pp. 24, 25. 3,199,782 8/1965Shinn 137-815 X 3,201,041 3 19 5 w l 1 7 g1 5 X 10 M. CARY NELSON,Przmaly Exammer. 3,226,023 12/1965 Horton 13781.5 X S, SCOTT, AssistantExaminer 3,244,370 4/1966 Colston 137-81.5 X

1. A FLUID SYSTEM COMPRISING, A PLURALITY OF FLUID DEVICES ADAPTED TO BEMAINTAINED IN ONE OF TWO STABLE STATES, EACH OF SAID FLUID DEVICESINCLUDING A FIRST AND SECOND FLUID AND DEVICES, EACH AND DEVICE HAVINGTWO INPUT PORTS, FIRST AND SECOND OUTPUT LEGS, SAID AND DEVICE PRODUCINGAN OUTPUT ON SAID FIRST LEG WHEN AN INPUT SIGNAL IS APPLIED TO ONE OFSAID INPUT PORTS, AND PRODUCING AN OUTPUT ON SAID SECOND LEG WHEN INPUTSIGNALS ARE APPLIED TO BOTH OF SAID INPUT PORTS, INCLUDING A FLUIDFLIP-FLOP HAVING A FLUID POWER SOURCE, TWO OUTPUT LEGS, A FIRST INPUTPORT CONNECTED TO SAID SECOND OUTPUT LEG OF SAID FIRST AND DEVICE, AND ASECOND INPUT PORT CONNECTED TO SAID SECOND OUTPUT LEG OF SAID SECOND ANDDEVICE, WITH THE FLUID FLOW FROM THE